1. Field of the Invention
The present invention relates to a circuit simulation apparatus and a circuit simulation method, in particular, a technique for performing circuit simulation in consideration of variations in transistor characteristics depending on the shape of the peripheral pattern of the target transistor.
2. Description of the Related Art
One prominent property of high-integration LSI transistors is that the transistor characteristics thereof vary depending on the peripheral pattern shape. The magnitude of applied stress, the implantation dose of impurities and actual finished dimensions of a particular transistor are influenced by the peripheral pattern shape of the particular transistor. Such pattern dependency of the transistor characteristics is enhanced with the miniaturization of the pattern, thereby possibly causing a circuit malfunction and lowering the fabrication yield.
The problem that the pattern dependency severely affects the transistor characteristics may be solved by adopting any of the two approaches described below in the design phase. A first approach is to perform a timing design by setting margins for the manufacturing variations as well as margins for the variations in transistor characteristics depending on the pattern shape. A second approach is to perform layout design so that designed pattern dimensions are not in the region in which the transistor characteristics largely vary. These two approaches, however, suffers from a problem of an excessive margin in the design phase, resulting in deterioration of timing convergence in the circuit design and increase in design TAT (Turn Around Time). In addition, these two approaches may lead to overestimation of the chip size. In other words, the above-mentioned general approaches inevitably sacrifice at least one of the design TAT and the chip size (in turn, the cost) in order to assure the design quality and to prevent the risk of lowering the yield. This is undesirable in terms of competitiveness of product LSIs.
To solve the problem of the pattern dependency of the transistor characteristics, it is effective to grasp the pattern dependency of the transistor characteristics in detail, to estimate the transistor characteristics with high accuracy, and to perform circuit design and circuit simulation based on the estimated transistor characteristics. If the transistor characteristics can be estimated with high accuracy, this eliminates the need for setting of excessive margins and thereby reducing the design TAT with improved timing convergence. The accurate estimation of the transistor characteristics allows designing the pattern dimensions in a region in which the transistor characteristics largely vary, reducing the chip size due to the improved flexibility in selecting pattern dimensions.
One parameter on which the inventor has focused to estimate the pattern dependency of the transistor characteristics with high accuracy is the dependency of the transistor characteristics on the gate spacing. The characteristics of a particular transistor depend on the gate spacing between adjacent transistors (that is, the distance between the gate of a particular transistor and the gate of the neighboring transistor). It is important to consider such dependency of the transistor characteristics on the gate spacing between adjacent transistors for accurately estimating the transistor characteristics.
The fact that the gate spacing between adjacent transistors affects the transistor characteristics is publicly known in Japanese Laid-Open Patent Application No. JP-A Heisei 11-284170. This application discloses that the effective gate length Leff of a particular transistor depends on the gate spacing defined in the design layout due to the proximity effect, and this influences the drain current of the particular transistor.
According to the inventors' consideration, however, there are various effects caused by the gate spacing between adjacent transistors on the transistor characteristics other than the variations in the effective gate length Leff, and thus the technique method disclosed in Japanese Laid-Open Patent Application No. JP-A Heisei 11-284170 is insufficient to perform accurate circuit simulation.